Smallest Transistor Ever

Atomically flat materials used to fabricate the world’s smallest transistor.

Schematic of the smallest field effect transistor ever made shows the components of the transistor. The current flowing through the atomically thin molybdenum disulfide (MoS2) material, placed between the source (S) and drain (D) terminals, is controlled by the voltage applied to the 1-nanometer-thick single-walled carbon nanotube (SWCNT), imbedded in zirconium dioxide (ZrO2) dielectric material. The atomic structure of the layers in the transmission electron microscope image on the right shows the nanotube embedded in the ZrO2 layer and resting on a silicon dioxide (SiO2) layer. The width of the nanotube is less than 1/1000th of the diameter of a red blood cell.

The Science

It has long been thought that building nanometer-sized transistors was impossible. Simply put, the physics and atomic structural imperfections couldn’t be overcome. However, scientists built fully functional, nanometer-sized transistors. They did so using atomically flat, two-dimensional molybdenum disulfide semiconductor and a single-walled carbon nanotube imbedded in zirconium dioxide.    

The Impact

Moore’s law states that the number of transistors per square inch on a microchip has doubled every year since they were invented. This has been realized by the ability to decrease the size of a transistor. However, when the gate length of the transistors approaches 5 nanometers, it was believed that our ability to continue to shrink a transistor size would reach its limit. Below this feature size, it was not clear how to build next-generation devices. The result of this research shows that it is feasible to continue to reduce the size of a transistor, all the way down to 1 nanometer.


The next generation of microelectronics will only be realized by finding ways to continue to reduce the size of a transistor. Since the introduction of integrated circuits, the observation referred to as Moore’s law has been met — about every year, the number of transistors per unit area has doubled continuously, which is a direct consequence of our ability to continue to decrease the size of a transistor. The gate length of a transistor is the defining parameter of the transistor size, and is presently about 20 nanometers in commercial electronic chips. It is not possible to shrink it below 5 nanometers using silicon. However, researchers have demonstrated that using the semiconducting material molybdenum disulfide (MoS2) and single-walled carbon nanotubes, the transistor gate length can be reduced to a record size of 1 nanometer. The team used these materials to fabricate a fully operational transistor. These novel materials are atomically uniform at a thickness down to a monolayer. In comparison to current materials, these newly discovered materials have lower dielectric constants, larger band gaps, and a larger carrier effective mass making them ideally matched to the device requirements. The characteristics of the nanometer-sized transistor have been measured and show a subthreshold swing ~65 mV/decade and On/Off current ratio ~106. This work demonstrated the shortest transistor ever and that Moore’s law can continue a while longer by proper engineering of the semiconductor material and device architecture.


Prof. Ali Javey
(510) 643-7263


U.S. Department of Energy (DOE), Office of Science (overall analysis of experimental/theoretical data, MoS2 materials processing/fabrication, and electron transport measurements) including support by the Molecular Foundry, an Office of Science national user facility; Applied Materials Inc. and Entegris, Inc. (A.B.S.); Office of Naval Research (J.P.L. and J.B.); Berkeley Fellowship for Graduate Studies and the National Science Foundation Graduate Fellowship Program (J.P.L.); Nanoelectronics Research Initiative South West Academy of Nanoelectronics Center and Chinese Academy of Sciences President’s International Fellowship Initiative (Q.W. and M.J.K.); SONIC (Systems on Nanoscale Information Fabrics) Research Center, one of six centers supported by the STARnet phase of the Focus Center Research Program, a Semiconductor Research Corporation program sponsored by the Microelectronics Advanced Research Corporation (MARCO) and Defense Advanced Research Projects Agency (G.P. and H.-S.P.W.); National Science Foundation Center for Energy Efficient Electronics Science (E3S) (A.J., H.S.P.W., and J.B.); and Samsung (A.J.). Resources at the Molecular Foundry, a DOE Office of Science national scientific user facility, were used.


S.B. Desai, S.R. Madhvapathy, A.B. Sachid, J.P. Llinas, Q. Wang, G.H. Ahn, G. Pitner, M.J. Kim, J. Bokor, C. Hu, H.S.P. Wong, and A. Javey, “MoS2 transistors with 1-nanometer gate lengths.” Science 354(6308), 99-102 (2016). [DOI: 10.1126/science.aah4698]

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